In limited volume production such as that found in the application specific integrated circuit (ASIC) realm, potential design improvements are difficult to assess because of the low volumes. While there are many techniques for testing integrated chips, current testing methodology provides little information useful to the designer of integrated circuits in terms of determining the effects of different process technology device library elements or different latch circuit implementations on integrated circuit performance. Evaluations can be performed using test chips. However test chips are expensive to design and fabricate and cannot normally be run in sufficient volume in limited volume production scenarios such as found in the ASIC realm.
Therefore, there is a need for an inexpensive methodology for characterization of process technology device library elements and latch circuits.